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preliminary cyw43364 single-chip ieee 802.11 b/g/n mac/ baseband/radio cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-14781 rev. *c revised friday, november 18, 2016 the cypress cyw43364 is a highly integrated single-chip solution and offers the lowest rbom in th e industry for internet of thi ngs (iot) and a wide range of other portable devices. the chip incl udes a 2.4 ghz wlan ieee 802.11 b/g/n mac/baseband/radio. in addition, it integrates a power amplifier (pa) that meets the ou tput power requirements of most handheld systems, a low-noise a mplifier (lna) for best-in-class receiver sensitivity, and an internal transmit/receive (itr) rf switch, further reducing the overall so lution cost and printed circuit board area. the wlan host interface supports gspi and sdio v2.0 modes, provid ing a raw data transfer rate up to 200 mbps when operating in 4-bit mode at a 50 mhz bus frequency. using advanced design techniques and process technology to reduce active and idle power, the cyw43364 is designed to address the needs of highly mobile devices that require minimal power co nsumption and compact size. it includes a power management unit that simplifies the system power topo logy while maximizing battery life. cypress part numbering scheme cypress is converting the acquired iot part numbers from broadcom to the cypress par t numbering scheme. due to this conversion, there is no change in form, fit, or function as a result of offe ring the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in cypress documents, go to http://www.cypress.com/glossary . figure 1. cyw43364 system block diagram table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number BCM43364 cyw43364 BCM43364kubg cyw43364kubg BCM43364kubgt cyw43364kubgt vddio vbat 2.4 ? ghz ? wlan ? tx/rx wlan ? host ? i/f wl_reg_on sdio*/spi wl_host_wake bpf clk_req ref_clk (19.2, ? 26, ? or ? 37.4 ? mhz) cyw43364
preliminary cyw43364 document number: 002-14781 rev. *c page 2 of 68 features ieee 802.11x key features single-band 2.4 ghz ieee 802.11b/g/n. support for 2.4 ghz cypress turboqam ? data rates (256- qam) and 20 mhz channel bandwidth. integrated itr switch supports a single 2.4 ghz antenna. supports explicit ieee 802.11n transmit beamforming. tx and rx low-density parity check (ldpc) support for improved range and power efficiency. supports standard sdio v2.0 and gspi host interfaces. supports space-time block coding (stbc) in the receiver. integrated arm cortex-m3 processor and on-chip memory for complete wlan sub system functionality, minimizing the need to wake up the applications processor for standard wlan functions. this allows for further minimization of power consumption, while maintaining the ability to field-upgrade with future features. on-chip memory includes 512 kb sram and 640 kb rom. onedriver ? software architecture for easy migration from existing embedded wlan. general features support diversity antenna. supports a battery voltage rang e from 3.0v to 4.8v with an internal switching regulator. programmable dynamic power management. 4 kbit one-time programmable (otp) memory for storing board parameters. can be routed on low-cost 1-x-1 pcb stack-ups. 74-ball wlbga package (4.87 mm 2.87 mm, 0.4 mm pitch). security: ? wpa and wpa2 (personal) support for powerful encryption and authentication. ? aes in wlan hardware for fast er data encr yption and ieee 802.11i compatibility. ? reference wlan subsystem provides cisco compatible ex- tensions (ccx, ccx 2.0, cc x 3.0, ccx 4.0, ccx 5.0). ? reference wlan subsystem prov ides wi-fi protected setup (wps). worldwide regulatory support: gl obal products supported with worldwide homologated design. iot resources cypress provides a wealth of data at http://www.cypress.co m/internet-things-iot to help you to select the right iot device for your design, and quickly and effectively integrat e the device into your design. cypress pr ovides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ( http://community.cypress.com/ ).
document number: 002-14781 rev. *c page 3 of 68 preliminary cyw43364 contents 1. overview ........................................................................ 4 1.1 overview ............................................................... 4 1.2 features ................................................................ 5 1.3 standards compliance .......................................... 5 2. power supplies an d power management ................... 6 2.1 power supply topology ........................................ 6 2.2 cyw43364 pmu features .. .............. ........... ......... 6 2.3 wlan power management . .............. ........... ......... 9 2.4 pmu sequencing ............. .............. .............. ......... 9 2.5 power-off shutdown ........................................... 10 2.6 power-up/power-down/rese t circuits ............... 10 3. frequency references ............................................... 11 3.1 crystal interface and clock generation .............. 11 3.2 tcxo .................................................................. 12 3.3 external 32.768 khz low-power oscillator ......... 13 4. wlan system interfaces ........................................... 14 4.1 sdio v2.0 ............................................................ 14 4.2 generic spi mode ............................................... 15 5. wireless lan mac and phy ..................................... 24 5.1 mac features ..................................................... 24 5.2 phy description ............ ...................................... 26 6. wlan radio subsystem ............................................ 28 6.1 receive path ....................................................... 28 6.2 transmit path ...................................................... 28 6.3 calibration ........................................................... 28 7. cpu and global functions ........................................ 29 7.1 wlan cpu and memory subsystem ...... ............ 29 7.2 one-time programmable memory ...................... 29 7.3 gpio interface .................................................... 29 7.4 external coexistence interface ........................... 30 7.5 jtag interface ................................................... 32 7.6 uart interface ................................................... 32 8. pinout and signal descriptions ................................ 33 8.1 ball map .............................................................. 33 8.2 wlbga ball li st in ball number order with x-y coordinates ................................................. 34 8.3 wlbga ball list ordered by ball name ............. 37 8.4 signal descriptions .............................................. 38 8.5 wlan gpio signals and strapping options ...... 41 8.6 chip debug options ............................................ 41 8.7 i/o states ............................................................ 42 9. dc characteristics ..................................................... 44 9.1 absolute maximum ratings ................................. 44 9.2 environmental ratings ........................................ 44 9.3 electrostatic discharge s pecifications ................ 45 9.4 recommended operating conditions and dc characteristics ............................................. 45 10. wlan rf specifications .......................................... 47 10.1 2.4 ghz band general rf specifications ......... 47 10.2 wlan 2.4 ghz receiver performance specifications ................................................... 48 10.3 wlan 2.4 ghz transmitter performance specifications ................................................... 51 10.4 general spurious emissions specifications ...... 52 11. internal regulator electri cal specifications .......... 53 11.1 core buck switching re gulator ......................... 53 11.2 3.3v ldo (ldo3p3) ......................................... 54 11.3 cldo ................................................................ 55 11.4 lnldo .............................................................. 56 12. system power consumption ................................... 57 12.1 wlan current consumption ............................. 57 13. interface timing and ac characteristics ............... 58 13.1 sdio default mode timi ng ............................... 58 13.2 sdio high-speed mode ti ming .......... .............. 59 13.3 gspi signal timing ..... ....................................... 60 13.4 jtag timing ..................................................... 61 14. power-up sequence and timing ............................. 62 14.1 sequencing of reset and regulator control signals ............ .............. .............. .............. ........ 62 15. package information ............ .............. .............. ........ 63 15.1 package thermal characte ristics ....... .............. 63 16. mechanical information ........................................... 64 17. ordering information ................................................ 66 document history .......................................................... 67
document number: 002-14781 rev. *c page 4 of 68 preliminary cyw43364 1. overview 1.1 overview the cypress cyw43364 provides the highest level of integrat ion for iot and wireless automat ion system, with integrated ieee 802.11 b/g/n. it provides a small form-fac tor solution with minimal exte rnal components to drive do wn cost for mass volumes and allows for handheld device flexibility in size, form, and func tion. the cyw43364 is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. figure 2 on page 4 shows the interconnection of all the major physical blocks in the cyw43364 and their associated external interfaces, which are described in greater detail in subsequent sections. figure 2. cyw43364 block diagram common and radio digital swreg ldox2 lpo xtal osc. bpf wlan sdio gspi jtag* arm cm3 backplane bt- wlan eci wdt otp gpio uart jtag* ram rom pmu control mac lnpphy radio ahb bus matrix cortex m3 etm jtag* sdp ram rom patch interctrl dma bus arb arm ip wd timer sw timer gpio ctrl apb sdio or gspi debug ieee 802.11a/b/g/n gpio uart 2.4 ghz 2.4 ghz pa lna power supply sleep clk xtal ahb to apb bridge ahb supported over sdio jtag supported over sdio por wl_reg_on
document number: 002-14781 rev. *c page 5 of 68 preliminary cyw43364 1.2 features the cyw43364 supports the following wlan features: ieee 802.11b/g/n single-band radio with an internal power amplifier, lna, and t/r switch on-chip wlan driver execution capable of supporting ieee 802.11 functionality wlan host interface options: ? sdio v2.0, including default and high-speed timing. ? gspi?up to a 50 mhz clock rate 1.3 standards compliance the cyw43364 supports the following standards: ieee 802.11n?handheld device class (section 11) ieee 802.11b ieee 802.11g ieee 802.11d ieee 802.11h ieee 802.11i the cyw43364 will support the following future drafts/standards: ieee 802.11r ? fast roaming (between aps) ieee 802.11k ? resource management ieee 802.11w ? secure management frames ieee 802.11 extensions: ieee 802.11e qos enhancements (as per the wmm specification is already supported) ieee 802.11i mac enhancements ieee 802.11r fast roaming support ieee 802.11k radio resource measurement the cyw43364 supports the following securi ty features and proprietary protocols: security: ? wep ? wpa personal ? wpa2 personal ? wmm ? wmm-ps (u-apsd) ? wmm-sa ? wapi ? aes (hardware accelerator) ? tkip (host-computed) ? ckip (sw support) proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 ieee 802.15.2 coexistence complianc e ? on silicon solution compli ant with ieee 3-wire requirements.
document number: 002-14781 rev. *c page 6 of 68 preliminary cyw43364 2. power supplies and power management 2.1 power supply topology one buck regulator, multiple ldo regulators, and a power managem ent unit (pmu) are integrated into the cyw43364. all regulators are programmable via the pmu to simplify the power supply. a single vbat (3.0v to 4.8v dc maximum) and vddio supply (1.8v to 3.3v) can be used, with all additional voltages being provide d by the regulators in the cyw43364. the wl_reg_on control signal is used to po wer up the regulators and take the respective circuit blocks out of reset. the cbuck cldo and lnldo power up when any of the reset signals are dea sserted. all regulators are powered down only when wl_reg_on is deasserted. the cldo and lnldo can be turned on and off based on the dynamic demands of the digital baseband. the cyw43364 allows for an extremely lo w power-consumption mode by completely sh utting down the cbuck, cldo, and lnldo regulators. when in this state, lpldo1 provides the cyw43364 with all required vo ltage, further reducing leakage currents. notes : vbat should be connected to the ldo_vddbat5v and sr_vddbat5v pins of the device. vddio should be connected to the sys_vddio and wcc_vddio pins of the device. 2.2 cyw43364 pmu features the pmu supports the following: vbat to 1.35vout (170 ma nominal, 370 ma maxi mum) core-buck (cbuck) switching regulator vbat to 3.3vout (250 ma nominal, 450 ma maximum 800 ma peak maximum) ldo3p3 1.35v to 1.2vout (100 ma nominal, 150 ma maximum) lnldo 1.35v to 1.2vout (80 ma nominal, 200 ma maximum) cldo with bypass mode for deep sleep additional internal ldos (not externally accessible) pmu internal timer auto-calibration by the crystal clock for prec ise wake-up timing from extremely low power-consumption mode. figure 3 on page 7 and figure 4 on page 8 show the typical power topology of the cyw43364.
document number: 002-14781 rev. *c page 7 of 68 preliminary cyw43364 figure 3. typical power topology (1 of 2) mini ? pmu wl ? rf?logen wl ? rf?rx ? lna wl ? rf?adc ? ref wl ? rf?tx wl ? rf?afe ? and ? tia wl ? rf?xtal internal ? vcoldo 80 ? ma ? (nmos) internal ? rxldo 10 ? ma ? (nmos) internal ? adcldo 10 ? ma ? (nmos) internal ? txldo 80 ? ma ? (pmos) internal ? afeldo 80 ? ma ? (nmos) lnldo (100 ? ma) 1.2v 1.2v 1.2v 1.2v cl ? ldo peak: ? 200 ? ma avg: ? 80 ? ma (bypass ? in ? deep \ sleep) core ? buck ? regulator ? peak: ? 370 ? ma avg: ? 170 ? ma lpldo1 (5 ? ma) 2.2 ? uh 0603 1.35v 1 . 1 v 1.2v 1.2v sr_vddbat5v vdd1p35 ldo_vdd_1p5 4.7 ? uf 0402 sr_pvss sr_vlx o_wl_resetb wl_reg_on wcc_vddio wcc_vddio (40 ? ma) pmu_vss gnd sr_vbat5v vbat int_sr_vbat cyw43364 1.2v vbat: operational: 2.4v?4.8v performance: 3.0v?4.8v absolute ? maximum: 5.5v vddio operational: 1.8v?3.3v 600 ? @ 100 ? mhz 2.2 ? uf 0402 0.1 ? uf 0201 wlrf_xtal_ vdd1p2 wl ? rf?tx ? mixer ? and ? pa wl ? rf?rfpll ? pfd ? and ? mmd 10 ? ma ? average, ? > ? 10 ? ma ? at ? start \ up vout_lnldo 2.2 ? uf 0402 vddc1 vddc2 (avs) vout_cldo 1.3v, ? 1.2v, ? or ? 0.95v wlan/clb/top, ? always ? on wl ? otp wl ? digital ? and ? phy wl ? vddm ? (sroms ? & ? aos) mini ? pmu ? is ? placed ? in ? wl ? radio vbat supply ? ball supply ? bump/pad ground ? ball ground ? bump/pad external ? to ? chip power ? switch no ? power ? switch no ? dedicated ? power ? switch, ? but ? internal ? power \ down ? modes ? and ? block \ specific ? power ? switches (320 ? ma) sw1 wlan ? reset ? balls
document number: 002-14781 rev. *c page 8 of 68 preliminary cyw43364 figure 4. typical power topology (2 of 2) cyw43364 1.8v, ? 2.5v, ? and ? 3.3v 4.7 ? uf 0402 ldo3p3 ? with back \ power ? protection (peak ? 450 \ 800 ? ma 200 ? ma ? average) vout_3p3 3.3v ldo_ vddbat5v vbat wlrf_pa_vdd 2.5v ? cap \ less ? lnldo (10 ? ma) wl ? rf?pa ? (2.4 ? ghz) wl ? otp ? 3.3v wl ? rf?adc, ? afe, ? logen, ? lna, ? nmos ? mini \ pmu ? ldos 6.4 ? ma 480 ? to ? 800 ? ma supply ? ball external ? to ? chip power ? switch no ? power ? switch no ? dedicated ? power ? switch, ? but ? internal ? power \ down ? modes ? and ? block \ specific ? power ? switches 1 ? uf 0201 wl ? bbpll/dfll vout_3p3 6.4 ? ma
document number: 002-14781 rev. *c page 9 of 68 preliminary cyw43364 2.3 wlan power management the cyw43364 has been designed with the stringen t power consumption requirements of mob ile devices in mind. all areas of the chip design are optimized to minimize power consumption. silicon processes and cell libraries were chosen to reduce leakage cur rent and supply voltages. additionally, the cyw 43364 integrated ram is a high volatile memory with dynamic clock control. the domina nt supply current consumed by the ram is leakage current on ly. additionally, the cyw43364 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provides si gnificant power savings by putting the cyw43364 into various power management states appropriate to the operating environment and the activiti es that are being performed. the power management unit enables and disables internal regulators, swit ches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. power-u p sequences are fully programmable. configurable, free-running counte rs (running at the 32.768 khz lpo clock) in the pmu sequence r are used to turn on/turn off individual regulators and powe r switches. clock speeds are dynamically changed (or gated altogethe r) for the current mode. slower clock speeds are used wherever possible. the cyw43364 wlan power states are described as follows: active mode: all wlan blocks in the cyw43364 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled a nd put in the most efficient m ode based on the load current. c lock speeds are dynamically adjus ted by the pmu sequencer. doze mode: the radio, analog domains, and most of the linear regulators are powered down. the rest of the cyw43364 remains powered up in an idle state. all main cl ocks (pll, crystal oscillator) are shut down to reduce active power to the minimum. the 32.768 khz lpo clock is available only for the pmu sequencer. th is condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in doze mode, the primary power consumed is due to leakage current. deep-sleep mode: most of the chip, including analog and digital domains, and most of the regula tors are powered off. logic stat es in the digital core are saved and preserved to retention memory in the always-on doma in before the digital core is powered off. to avoid lengthy hardware reinitialization, t he logic states in the digital core are re stored to their pre-deep-sleep settings whe n a wake- up event is triggered by an external interrupt, a host resume through the sdio bus, or by the pmu timers. power-down mode: the cyw43364 is effectively powered off by shu tting down all internal regulators. the chip is brought out of this mode by external logic re-enabling the internal regulators. 2.4 pmu sequencing the pmu sequencer is used to minimize system power consumption. it enables and disabl es various system resources based on a computation of required resources and a table that describes th e relationship between resources and the time required to enable and disable them. resource requests can derive from several sources: clock re quests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource re quest timers. the pmu sequencer maps clock requests into a set o f resources required to pro duce the requested clocks. each resource is in one of the following four states: enabled disabled transition_on transition_off the timer value is 0 when the resource is enabled or disabled a nd nonzero during state transition. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that the resource must be enabled or disabled. that timer decrements on each 32.768 khz pmu clock. when it reac hes 0, the state changes fr om transition_off to disabled or transition_on to enabled. if the time_on value is 0, the res ource can transition immediately from disabled to enabled. similarly, a time_off value of 0 indi cates that the resource can transition immediately from enabled to disabled. the terms enable sequence and disable sequence refer to either the immediate transition or the timer load-decrement sequence. during each clock cycle, t he pmu sequencer performs the following actions: computes the required resource set based on requests and the resource dependency table. decrements all timers whose values are nonzero. if a timer reac hes 0, the pmu clears the resourcepending bit for the resource and inverts the resourcestate bit. compares the request with the current resource status and determines which resources must be enabled or disabled. initiates a disable sequence for each resource that is enabl ed, no longer being requested, and has no powered-up dependents. initiates an enable sequence for each resource that is disabled , is being requested, and has all of its dependencies enabled.
document number: 002-14781 rev. *c page 10 of 68 preliminary cyw43364 2.5 power-off shutdown the cyw43364 provides a low-power shutdown feature that allows the device to be tu rned off while the host, and any other device s in the system, remain operational. when the cyw43364 is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the cyw43364 to be effectively off while keeping the i/o pins powered so that they do not dr aw extra current from any other devices connected to the i/o. during a low-power shutdown state, provided vddio remains appli ed to the cyw43364, all outputs are tristated, and most input signals are disabled. input volta ges must remain within the limits defined for norma l operation. this is done to prevent curren t paths or create loading on any digital signals in the system, and enable s the cyw43364 to be fully integrated in an embedded device a nd to take full advantage of the lowest power-savings modes. when the cyw43364 is powered on from this state, it is the same as a normal powe r-up, and the device does not retain any information about its state from before it was powered down. 2.6 power-up/power -down/reset circuits the cyw43364 has two signals (see ta b l e 2 ) that enable or disable the wlan circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagrams of these signals and the r equired power-up sequences, see section 14.: ?power-up sequence and timing,? on page 62 . table 2. power-up/power-down/reset control signals signal description wl_reg_on this signal is used by the pmu to power-up the wlan se ction. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by def ault. it can be disabled through programming.
document number: 002-14781 rev. *c page 11 of 68 preliminary cyw43364 3. frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference driven by a temperatur e-compensated crystal oscillator (tcxo) signal ma y be used. no software settings are required t o differentiate between the two. in addition, a low-power o scillator (lpo) is provided for lower power mode timing. 3.1 crystal interface and clock generation the cyw43364 can use an external crystal to provide a frequency reference. the reco mmended configuration for the crystal oscill ator, including all external components, is shown in figure 5 . consult the reference schematics for the latest configuration. figure 5. recommended oscillator configuration the cyw43364 uses a fractional-n synthesizer to generate the radi o frequencies, clocks, and data/packet timing so that it can o perate using numerous frequency references. the frequency reference can be an external source such as a tcxo or a crystal interfaced directly to the cyw43364. the default frequency reference setting is a 37.4 mhz crystal or tcxo. the signal requirements and characteristics for the crys tal interface are shown in table 3 on page 12 . note: although the fractional-n synthesizer can support many refe rence frequencies, frequencies other than the default require support to be added in the driver, plus additional ext ensive system testing. contact cypress for further details. 12 ? 27 pf 12 ? 27 pf wlrf_xtal_xon wlrf_xtal_xop c c r note : resistor value determined by crystal drive level. see reference schematics for details.
document number: 002-14781 rev. *c page 12 of 68 preliminary cyw43364 3.2 tcxo as an alternative to a crystal, an external precision tcxo can be used as the frequency reference, provided that it meets the p hase noise requirements listed in table 3 on page 12 . if the tcxo is dedicated to driving the cyw43364, it should be co nnected to the wlrf_xtal_xop pin through an external capacitor with value ranges from 200 pf to 1000 pf as shown in figure 6 . figure 6. recommended circuit to use with an external dedicated tcxo table 3. crystal oscillator and external clock requirements and performance parameter conditions/notes crystal external frequency refer- ence units min. typ. max. min. typ. max. frequency ? ? 37.4 a a. the frequency step size is approximately 80 hz. the cyw43364 does not auto-detect the reference clock frequency; the frequenc y is specified in the software and/or nvram file. ??? ?mhz crystal load capacitance ? ? 12 ? ? ? ? pf esr ? ? ? 60 ? ? ? ? input impedance (wlrf_xtal_xop) resistive ? ? ? 10k 100k ? ? capacitive ? ? ? ? ? 7 pf wlrf_xtal_xop input voltage ac-coupled analog signal ? ? ? 400 b b. to use 256-qam, a 800 mv minimum voltage is required. ? 1260 mv p-p wlrf_xtal_xop input low level dc-coupled digital signal ? ? ? 0 ? 0.2 v wlrf_xtal_xop input high level dc-coupled digital signal ? ? ? 1.0 ? 1.26 v frequency tolerance initial + over temperature ? ?20 ? 20 ?20 ? 20 ppm duty cycle 37.4 mhz clock ? ? ? 40 50 60 % phase noise c, d, e (ieee 802.11 b/g) c. for a clock reference other than 37.4 mhz, 20 log10(f/37.4) db should be added to the limits, where f = the reference clock frequency in mhz. d. phase noise is assumed flat above 100 khz. e. the cyw43364 supports a 26 mhz reference clock sharing option. see the phase noise requirement in the table. 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?129 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?136 dbc/hz phase noise c, d, e (ieee 802.11n, 2.4 ghz) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?134 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?141 dbc/hz phase noise c, d, e (256-qam) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?140 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?147 dbc/hz tcxo nc 200 pf ? 1000 pf wlrf_xtal_xop wlrf_xtal_xon
document number: 002-14781 rev. *c page 13 of 68 preliminary cyw43364 3.3 external 32.768 khz low-power oscillator the cyw43364 uses a secondary low-frequency sleep clock for low-power mode timing. either the internal low-precision lpo or an external 32.768 khz precision oscillator is required. the internal lpo frequency range is approximately 33 khz 30% over proce ss, voltage, and temperature, which is adequate for some applications. however, one trade- off caused by this wide lpo tolerance is a small current consumption in crease during power save mode that is incurred by the need to wake up earlier to avoid missing beac ons. whenever possible, the preferred approach is to use a precision external 32.768 khz clock that meets the requirements listed in table 4 on page 13 . note: the cyw43364 will auto-detect the lp o clock. if it senses a clock on the ext_sleep_ clk pin, it will use that clock. if it doesn't sense a clock, it will use its own internal lpo. to use the internal lpo: tie ext_sleep_clk to ground. do not le ave this pin floating. to use an external lpo: connect the external 32.768 khz clock to ext_sleep_clk. table 4. external 32.768 kh z sleep-clock specifications parameter lpo clock units nominal input frequency 32.768 khz frequency accuracy 200 ppm duty cycle 30?70 % input signal amplitude 200?3300 mv, p-p signal type square wave or sine wave ? input impedance a a. when power is applied or switched off. >100 k ? <5 pf clock jitter <10,000 ppm
document number: 002-14781 rev. *c page 14 of 68 preliminary cyw43364 4. wlan system interfaces 4.1 sdio v2.0 the cyw43364 wlan section supports sdio version 2.0. for both 1- bit (25 mbps) and 4-bit modes (100 mbps), as well as high speed 4-bit mode (50 mhz clocks?200 mbps). it has the ability to map t he interrupt signal on a gpio pin. this out-of-band interrupt s ignal notifies the host when the wlan device wants to turn on the sdio interface. the abilit y to force control of the gated clocks fr om within the wlan chip is also provided. sdio mode is enabled using the strapping option pins. see table 11 on page 41 for details. three functions are supported: function 0 standard sdio function. the maximum block size is 32 bytes. function 1 backplane function to access the internal system-on-a- chip (soc) address space. the maximum block size is 64 bytes. function 2 wlan function for efficient wlan packet tran sfer through dma. the maximum block size is 512 bytes. 4.1.1 sdio pin descriptions figure 7. signal connections to sdio host (sd 4-bit mode) figure 8. signal connections to sdio host (sd 1-bit mode) table 5. sdio pin descriptions sd 4-bit mode sd 1-bit mode gspi mode data0 data line 0 data data line do data output data1 data line 1 or interrupt irq interrupt irq interrupt data2 data line 2 nc not used nc not used data3 data line 3 nc not used cs card select clk clock clk clock sclk clock cmd command line cmd command line di data input sd ? host cmd dat[3:0] clk cyw43364 sd ? host cmd clk data irq cyw43364
document number: 002-14781 rev. *c page 15 of 68 preliminary cyw43364 4.2 generic spi mode in addition to the full sdio mode, the cyw43364 includes the opt ion of using the simplified gene ric spi (gspi) interface/protoc ol. characteristics of the gspi mode include: up to 50 mhz operation fixed delays for responses and data from the device alignment to host gspi frames (16 or 32 bits) up to 2 kb frame size per transfer little-endian and big-endian configurations a configurable active edge for shifting packet transfer through dma for wlan the gspi mode is enabled using the strapping option pins. see table 11 on page 41 for details. figure 9. signal connections to sdio host (gspi mode) sd ? host di sclk do irq cs cyw43364
document number: 002-14781 rev. *c page 16 of 68 preliminary cyw43364 4.2.1 spi protocol the spi protocol supports both 16-bit and 32-bit word op eration. byte endianess is supported in both modes. figure 10 and figure 11 on page 17 show the basic write and write/read commands. figure 10. gspi write protocol
document number: 002-14781 rev. *c page 17 of 68 preliminary cyw43364 figure 11. gspi read protocol
document number: 002-14781 rev. *c page 18 of 68 preliminary cyw43364 command structure the gspi command structure is 32 bits. the bit positions and definitions are shown in figure 12 . figure 12. gspi command structure write the host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the cs going low . the following bits are clocked out on the falling edge of the gspi clock. the device samples the data on the active edge. write/read the host reads on the rising edge of the clock requiring data fr om the device to be made available before the first rising-cloc k edge of the data. the last clock edge of the fixed delay word can be used to represent the first bit of the following data word. thi s allows data to be ready for the first clock edge without relying on asynchronous delays. read the read command always follows a separate write to set up the wl an device for a read. this command differs from the write/read command in the following respects: a) chip selects go high be tween the command/address and the data, and b) the time interval between the command/address is not fixed. 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0 01 C func 1 10 C func 2 11 C func 3 command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes 0 10 27 11 packet length - 11bits * address C 17 bits f1 f0 c a function no: 00 C func 0: all spi-specific registers 01 C func 1: registers and memories belonging to other blocks in the chip (64 bytes max) 10 C func 2: dma channel 1. wlan packets up to 2048 bytes. 11 C func 3: dma channel 2 (optional). packets up to 2048 bytes. command : 0 C read 1 C write bcm_spid command structure 28 29 30 31 access : 0 C fixed address 1 C incremental address * 11h0 = 2048 bytes
document number: 002-14781 rev. *c page 19 of 68 preliminary cyw43364 status the gspi interface supports status notification to the host after a read/write transaction. this status notificat ion provides i nformation about packet errors, protocol errors, available packets in the rx queue, etc. the status info rmation helps reduce the number of interrupts to the host. the status-reporting feature can be switched off using a regist er bit, without any timing overhead. the gspi bus timing for read/write transactions with and wit hout status not ification are as shown in figure 13 below and figure 14 on page 20 . see table 6 on page 20 for information on status-field details. figure 13. gspi signal timing without status c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits sclk mosi c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits miso response delay d1 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits cs c31 c30 c1 c0 d31 d30 d1 d0 c31 c30 c1 c0 d31 d30 d1 d0 command 32 bits write data 16*n bits c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay d1 c31 c30 c0 d31 d30 d0 command 32 bits read data 16*n bits response delay d1 write write-read read cs sclk mosi miso cs sclk mosi
document number: 002-14781 rev. *c page 20 of 68 preliminary cyw43364 figure 14. gspi signal timing with status (response delay = 0) 4.2.2 gspi host-device handshake to initiate communication through the gspi af ter power-up, the host needs to bring up t he wlan chip by writing to the wake-up w lan register bit. writing a 1 to this bit will start up the necessary crystals and plls so that the cyw43364 is ready for data tran sfer. the device can signal an interrupt to the host indicating that t he device is awake and ready. this procedure also needs to be follo wed for waking up the device in sleep mode. the device can interrupt the host using the wlan irq line whenever it has any information t o pass to the host. on getting an interrupt, the host needs to read the interrupt and/or status r egister to determine the cause o f the interrupt and then take necessary actions. table 6. gspi status field details bit name description 0 data not available the requested read data is not available. 1 underflow fifo underflow occurred due to current (f2, f3) read command. 2 overflow fifo overflow occurred due to current (f1, f2, f3) write command. 3 f2 interrupt f2 channel interrupt 5 f2 rx ready f2 fifo is ready to receive data (fifo empty). 7reserved ? 8 f2 packet available packet is available/ready in f2 tx fifo. 9:19 f2 packet length length of packet available in f2 fifo c31 c0 d31 d1 d0 read data 16*n bits s0 s31 status 32 bits c31 c0 d31 d1 d0 command 32 bits read data 16*n bits s0 s31 status 32 bits c31 s0 c1 c0 d31 s31 d1 d0 command 32 bits write data 16*n bits s1 status 32 bits c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 s0 c1 c0 d31 s31 d1 d0 s1 c31 s0 c1 c0 d31 s31 d1 d0 s1 command 32 bits write write-read read miso cs sclk mosi miso cs sclk mosi miso cs sclk mosi
document number: 002-14781 rev. *c page 21 of 68 preliminary cyw43364 4.2.3 boot-up sequence after power-up, the gspi host needs to wait 50 ms for the device to be out of reset. for this, the host needs to poll with a re ad command to f0 address 0x14. address 0x14 contains a predefined bit patte rn. as soon as the host gets a response back with the correct r egister content, it implies that the device has powered up and is out of reset. after that, the host needs to set the wake-up wlan bit (f0 reg 0x00 bit 7). wake-up wlan turns the pll on; however, the pll do esn't lock until the host programs the pll registers to set the crystal frequency. for the first time after power-up, the host needs to wait for the availability of the low-power clock inside the device. once i t is available, the host needs to write to a pmu register to set the crystal frequency. this will turn on the pll. after the pll is locked, the chipactive interrupt is issued to the host. this indicates device awake/ready status. see table 7 for information on gspi registers. in table 7 , the following notation is used for register access: r: readable from host and cpu w: writable from host u: writable from cpu table 7. gspi registers address register bit access default description x0000 word length 0 r/w/u 0 0: 16-bit word length 1: 32-bit word length endianess 1 r/w/u 0 0: little endian 1: big endian high-speed mode 4 r/w/u 1 0: normal mode. sample on spiclk rising edge, output on falling edge. 1: high-speed mode. sample and output on rising edge of spiclk (default). interrupt polarity 5 r/w/u 1 0: interrupt active polarity is low. 1: interrupt active polarity is high (default). wake-up 7 r/w 0 a write of 1 denotes a wake -up command from host to device. this will be followed by an f2 interrupt from the gspi device to host, indicating device awake status. x0002 status enable 0 r/w 1 0: no status sent to host after a read/write. 1: status sent to host after a read/write. interrupt with status 1 r/w 0 0: do not interrupt if status is sent. 1: interrupt host even if status is sent. x0003 reserved ? ? ? ? x0004 interrupt register 0r/w 0 requested data not available. cleared by writing a 1 to this location. 1 r 0 f2/f3 fifo underflow from the last read. 2 r 0 f2/f3 fifo overflow from the last write. 5 r 0 f2 packet available 6 r 0 f3 packet available 7 r 0 f1 overflow from the last write. x0005 interrupt register 5 r 0 f1 interrupt 6 r 0 f2 interrupt 7 r 0 f3 interrupt x0006, x0007 interrupt enable register 15:0 r/w/u 16'he0e7 particular interrupt is enabled if a corresponding bit is set. x0008 to x000b status register 31:0 r 32'h0000 same as status bit definitions
document number: 002-14781 rev. *c page 22 of 68 preliminary cyw43364 figure 15 on page 23 shows the wlan boot-up sequence from power-up to fi rmware download, including the initial device power-on reset (por) evoked by the wl_reg_on signal. after initial pow er-up, the wl_reg_on signal can be held low to disable the cyw43364 or pulsed low to induce a subsequent reset. note: the cyw43364 has an internal power-on reset (por) circuit. the device will be held in reset for a maximum of 3 ms after vddc and vddio have both passed the 0.6v threshold. x000c, x000d f1 info. register 0 r 1 f1 enabled 1 r 0 f1 ready for data transfer 13:2 r/u 12'h40 f1 maximum packet size x000e, x000f f2 info. register 0 r/u 1 f2 enabled 1 r 0 f2 ready for data transfer 15:2 r/u 14'h800 f2 maximum packet size x0014 to x0017 test read-only register 31:0 r 32'hfeedbe ad this register contains a pred efined pattern, which the host can read to determine if the gspi interface is working properly. x0018 to x001b test r/w register 31:0 r/w/u 32'h0000000 0 this is a dummy register w here the host can write some pattern and read it back to determine if the gspi interface is working properly. x001c to x001f response delay registers 7:0 r/w 0x1d = 4, other registers = 0 individual response delays for f0, f1, f2, and f3. the value of the registers is the number of byte delays that are introduced before data is shift ed out of the gspi interface during host reads. table 7. gspi registers (cont.) address register bit access default description
document number: 002-14781 rev. *c page 23 of 68 preliminary cyw43364 figure 15. wlan boot-up sequence < 1.5 ms after 15 ms 1 the reference clock is assumed to be up. access to pll registers is possible. 15 1 ms < 50 ms < 3 ms after a fixed delay following internal por going high, the device responds to host f0 (address 0x14) reads. vddio wl_reg_on vddc (from internal pmu) internal por device requests a reference clock. spi host interaction: host polls f0 (address 0x14) until it reads a predefined pattern. host sets wake-up-wlan bit and waits 15 ms 1 , the maximum time for reference clock availability. after 15 1 ms, the host programs the pll registers to set the crystal frequency. host downloads code. chip-active interrupt is asserted after the pll locks. vbat ramp time from 0v to 4.3v > 40 s 0.6v > 2 sleep clock cycles wl_irq 1 this wait time is programmable in sleep-clock increments from 1 to 255 (30 s to 15 ms).
document number: 002-14781 rev. *c page 24 of 68 preliminary cyw43364 5. wireless lan mac and phy 5.1 mac features the cyw43364 wlan mac supports features specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the salient features are listed below: transmission and reception of aggregated mpdus (a-mpdu). support for power management schemes, including wmm power-sav e, power-save multipoll (psmp) and multiphase psmp operation. support for immediate ack and block-ack policies. interframe space timing support, including rifs. support for rts/cts and cts-to-self frame sequences for protecting frame exchanges. back-off counters in hardware for supporting multiple priorities as specified in the wmm specification. timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware. hardware off-load for aes-ccmp, legacy wpa tkip, lega cy wep ciphers, wapi, and support for key management. programmable independent basic service set (ibss) or infrastructure basic service set functionality statistics counters for mib support. 5.1.1 mac description the cyw43364 wlan mac is designed to support high throughput operation with low-power consumption. in addition, several power-saving modes that have been implemented allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 16 on page 24 . figure 16. wlan mac architecture the following sections provide an overview of the important modules in the mac. embedded ? cpu ? interface host ? registers, ? dma ? engines tx \ fifo 32 ? kb wep wep, ? tkip, ? aes txe tx ? a \ mpdu rxe pmq psm shared ? memory 6 ? kb psm ucode memory ext \ ihr ifs tsf nav ihr ? bus shm ? bus mac \ phy ? interface rx \ fifo 10 ? kb rx ? a \ mpdu
document number: 002-14781 rev. *c page 25 of 68 preliminary cyw43364 psm the programmable state machine (psm) is a microcoded engine that provides most of the low-level control to the hardware to implement the ieee 802.11 specific ation. it is a microcontroller that is highly optimized for flow-control operations, which are predom- inant in implementations of communication protocols. the inst ruction set and fundamental operations are simple and general, whi ch allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microc ode memory. it uses the shared memory to obtain operands for instructions, as a dat a store, and to exchange data between both th e host and the mac data pipeline (via the sh m bus). the psm also uses a scratch-pad memory (similar to a register bank) to stor e frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines by programming internal hardware registers (ihr). these ihrs are collocated with the hardware functions they control and are accessed by the psm via the ihr bus. the psm fetches instructions from the microcode memory using an address determined by the program counter, an instruction liter al, or a program stack. for alu operations, t he operands are obtained from shared memory , scratch-pad memory, ihrs, or instruction literals, and the results are written into th e shared memory, scratch-pad memory, or ihrs. there are two basic branch instructions: conditional branches a nd alu-based branches. to better support the many decision point s in the ieee 802.11 algorithms, branches can depend on either readi ly available signals from the hardware modules (branch conditi on signals are available to the psm without polling th e ihrs) or on the results of alu operations. wep the wired equivalent privacy (wep) engine encapsulates all the ha rdware accelerators to perform the encryption and decryption, as well as the mic computation and verification. the accelerators implement the following cipher algorithms: legacy wep, wpa tkip, and wpa2 aes-ccmp. based on the frame type and association information, the psm dete rmines the appropriate cipher algorithm to be used. it supplie s the keys to the hardware engines from an on-chip key table. th e wep interfaces with the transm it engine (txe) to encrypt and compute the mic on transmit frames and the receive engine (rxe) to decrypt and verify the mic on receive frames. wapi is also supported. txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit f rames in the txfifo. it interfaces with wep module to encrypt frames and transfers the frames acro ss the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fi fos. the mac supports multiple logical queues to support traffi c streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to sched ule a queue from which the next frame is transmitted. once the fram e is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware t hat allows the rapid assembly of mpdus in to an a-mpdu for tr ansmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the receive engine (rxe) constitutes the receive data path of t he mac. it interfaces with the dma engine to drain the received frames from the rx fifo. it transfers bytes acro ss the mac-phy interface and interfaces with the wep module to decrypt frames. the decrypted data is stored in the rx fifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteri a such as receiver address, b ssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of t he containers, and disaggregate them into component mpdus. ifs the ifs module contains the timers required to determine interf rame space timing including rifs timing. it also contains multip le back-off engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. th e txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the back-off engines (for each access category) monitor channel acti vity, in each slot duration, to determine whether to contin ue or pause the back-off counters. when the back-of f counters reach 0, the txe gets notified so that it may commence frame transmissi on. in the event of multiple back-off counters decrementing to 0 at the same time, the hardware resolves the conflict based on poli cies provided by the psm.
document number: 002-14781 rev. *c page 26 of 68 preliminary cyw43364 the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power- saving mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep timer, whose count value is initi alized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires, the mac is restored to its func tional state. the psm updates the tsf timer based on the sleep duration, ensuring that the tsf is synchronized to the network. tsf the timing synchronization function (tsf) module maintains the tsf timer of the mac. it also ma intains the target beacon trans- mission time (tbtt). the tsf timer hardware, under the control of the psm, is capable of adopting timestamps received from beac on and probe response frames in order to ma intain synchronization with the network. the tsf module also generates trigger signals fo r events that are specified as offsets from the tsf timer, such as uplink and d ownlink transmission times used in psmp. nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the durati on field of mac frames. this ensures that the mac complies with the protection me chanisms specified in the standard. the hardware, under the control of the psm, maintains the nav ti mer and updates the timer appropriately based on received frame s. this timing information is provided to the ifs module, which uses it as a virtual carrier-sense indication. mac-phy interface the mac-phy interface consists of a data pa th interface to exchange rx/tx data from/to the phy. in addition, there is a program ming interface, which can be controlled either by the host or the psm to configure and control the phy. 5.2 phy description the cyw43364 wlan di gital phy is designed to co mply with ieee 802.11b/g/n si ngle stream to provide wireless lan connectivity supporting data rates from 1 mbps to 96 mbps fo r low-power, high-performance handheld applications. the phy has been designed to meet specification requirements in the presence of interference, radio nonlinearity, and impairmen ts. it incorporates efficient implementations of the filters, fft, and viterbi decoder al gorithms. efficient algorithms have been d esigned to achieve maximum throughput and reliability, including algorithm s for carrier sense/rejection, frequency/phase/timing acquisi tion and tracking, and channel estimation and tracking. the phy receiv er also contains a robust ieee 802.11b demodulator. the phy carrier sense has been tuned to provide high throug hput for ieee 802.11g/ieee 802.11b hybrid networks. 5.2.1 phy features supports the ieee 802.11b/ g/n single-stream standards. supports explicit ieee 802.11n transmit beamforming. supports optional greenfield mode in tx and rx. tx and rx ldpc for improved range and power efficiency. supports ieee 802.11h/d for worldwide operation. algorithms achieving low power, enhanced sensitivity, range, and reliability. automatic gain control scheme for blocking and nonblocking application scenarios for cellular applications. closed-loop transmit power control. designed to meet fcc and ot her regulatory requirements. support for 2.4 ghz cypress turboqam data rates and 20 mhz channel bandwidth.
document number: 002-14781 rev. *c page 27 of 68 preliminary cyw43364 figure 17. wlan phy block diagram the phy is capable of fully calibrating the rf front-end to extrac t the highest performance. on power-up, the phy performs a fu ll calibration suite to correct for iq mismatch and local oscillato r leakage. the phy also performs periodic calibration to compen sate for any temperature related drift, thus ma intaining high-performance over time. a clos ed-loop transmit control algorithm mainta ins the output power at its required level and can control tx power on a per-packet basis. filters ? and ? radio ? comp frequency ? and ? timing ? synch carrier ? sense, ? agc, ? and ? rx ? fsm radio ? control ? block filters ? and ? radio ? comp afe ? and ? radio mac ? interface buffers ofdm ? demodulate viterbi ? decoder tx ? fsm pa ? comp modulation ? and ? coding modulate/ spread frame ? and ? scramble fft/ifft cck/dsss ? demodulate descramble ? and ? deframe coex
document number: 002-14781 rev. *c page 28 of 68 preliminary cyw43364 6. wlan radio subsystem the cyw43364 includes an integrated wlan rf transceiver that has been optimized for use in 2.4 ghz wi reless lan systems. it is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism band. the transmit and receive sections include all on-chip filtering, mixing, and gain control functions. impro vements to the radio design include shared tx/rx baseba nd filters and high immunity to supply noise. figure 18 shows the radio functional block diagram. figure 18. radio functional block diagram 6.1 receive path the cyw43364 has a wide dynamic range, direct conversion receiver . it employs high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. 6.2 transmit path baseband data is modulated and upconverted to the 2.4 ghz ism ban d. a linear on-chip power amplif ier is included, which is capa ble of delivering high output powers while meet ing ieee 802.11b/g/n specificat ions without the need for an external pa. this pa is s upplied by an internal ldo that is directly supplied by vbat, thereby eliminating the need for a separat e paldo. closed-loop output pow er control is integrated. 6.3 calibration the cyw43364 features dynamic on-chip calib ration, eliminating process variation ac ross components. this enables the cyw43364 to be used in high-volume applications because calibration rout ines are not required during manufacturing testing. these calibr ation routines are performed periodically during normal radio operat ion. automatic calibration examples include baseband filter calib ration for optimum transmit and receive performance and loft calibration for leakage reduction. in addit ion, i/q calibration, r calibr ation, and vco calibration are performed on-chip. wl ? logen wl ? pll wlan ? bb clb voltage ? regulators wl ? pa wl ? pga wl ? tx ? g \ mixer wl ? txlpf wl ? rx ? g \ mixer slna wl ? g \ lna12 wl ? rxlpf wl ? atx wl ? grx wl ? gtx wl ? arx wl ? adc wl ? adc wl ? rxlpf wl ? dac wl ? dac wl ? txlpf wlrf_2g_elg wlrf_2g_rf 4 ? ~ ? 6 ? nh ? 10 ? pf recommend ? q ? = ? 40
document number: 002-14781 rev. *c page 29 of 68 preliminary cyw43364 7. cpu and global functions 7.1 wlan cpu and memory subsystem the cyw43364 includes an integrated arm co rtex-m3 processor with internal ram and rom. the arm cortex-m3 processor is a low-power processor that features low gat e count, low interrupt latency, and low- cost debugging. it is intended for deeply embe dded applications that require fast interrupt response features. the processor implements the arm architecture v7-m with support for the thumb-2 instruction set. arm cortex-m3 prov ides a 30% performance gain over arm7tdmi. at 0.19 w/mhz, the cortex-m3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. arm cortex-m3 uses multiple technologies to reduce cost thro ugh improved memory utilization, re duced pin overhead, and reduced silicon area. arm cortex-m3 supports independent buses for code and data access (icode/dcode and system buses). arm cortex- m3 supports extensive debug features including real-time tracing of program execution. on-chip memory for the cpu includes 512 kb sram and 640 kb rom. 7.2 one-time programmable memory various hardware configuration parameters may be stored in an internal 4096-bit one-time programmable (otp) memory, which is read by system software after a device reset. in addition, customer-specif ic parameters, including the system vendor id and the mac address, can be stored, depending on the specific board design. the initial state of all bits in an unprogra mmed otp device is 0. after any bit is pr ogrammed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with the cypress wlan manufacturing tes t tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. prior to otp memory programming, all values should be verified using the appropriate editable nv ram.txt file, which is provided with the reference board design package. docum entation on the otp development process is available on the cypress customer support portal ( http://community .cypress.com/ ). 7.3 gpio interface five general-purpose i/o (gpio) pins are available on the cyw4 3364 that can be used to connect to various external devices. gpios are tristated by default. subsequently, they can be programm ed to be either input or output pins via the gpio control reg ister. they can also be programmed to have in ternal pull-up or pull-down resistors. gpio_0 is normally used as a wl_host_wake signal. the cyw43364 supports 2-wire, 3-wir e, and 4-wire coexistence config urations using gpio_1 throu gh gpio_4. the signal functions of gpio_1 through gpio_4 are programmable to support the three coexistence configurations.
document number: 002-14781 rev. *c page 30 of 68 preliminary cyw43364 7.4 external coexistence interface the cyw43364 supports 2-wire, 3-wire, and 4- wire coexistence interfaces to enable si gnaling between the device and an external colocated wireless device in order to manage wireless medium shar ing for optimal performance. the external colocated device can be any of the following ics: gps, wim ax, lte, or uwb. an lte ic is us ed in this section for illustration. 7.4.1 2-wire coexistence figure 19 shows a 2-wire lte coexistence example. the follow ing definitions apply to the gpios in the figure: gpio_1: wlan_seci_tx output to an lte ic. gpio_2: wlan_seci_rx input from an lte ic. figure 19. 2-wire coexistence interface to an lte ic lte/ic uart_in uart_out note: wlan_seci_out and wlan_seci_in are multiplexed on the gpios. gpio_1 wlan_seci_tx wlan_seci_rx gpio_2 cyw43364
document number: 002-14781 rev. *c page 31 of 68 preliminary cyw43364 7.4.2 3-wire and 4-wire coexistence interfaces figure 20 and figure 21 show 3-wire and 4-wire lte coexistence examples, res pectively. the following definitions apply to the gpios in the figures: for the 3-wire coexistence interface: gpio_2: wlan priority output to an lte ic. gpio_3: lte_rx input from an lte ic. gpio_4: lte_tx input from an lte ic. for the 4-wire coexistence interface: gpio_1: wlan priority output to an lte ic. gpio_2: lte frame sync input from an lte ic. this gp io applies only to the 4-wire coexistence interface. gpio_3: lte_rx input from an lte ic. gpio_4: lte_tx input from an lte ic. figure 20. 3-wire coexistence interface to an lte ic figure 21. 4-wire coexistence interface to an lte ic lte/ic gpio_2 gpio_3 gpio_4 lte_rx lte_tx wlan priority cyw43364 lte/ic gpio_1 gpio_2 gpio_3 wlan priority lte_frame_sync lte_rx gpio_4 lte_tx cyw43364
document number: 002-14781 rev. *c page 32 of 68 preliminary cyw43364 7.5 jtag interface the cyw43364 supports the ieee 1149.1 jtag boundary scan standard over sdio for performing device package and pcb assembly testing during manufactur ing. in addition, the jtag interface allows cy press to assist customers by using proprietary debug and characterization test tools during board bring-up. therefore, it is highly recommended to pr ovide access to the jtag pins b y means of test points or a header on all pcb designs. 7.6 uart interface one uart interface can be enabled by software as an alternate fu nction on the jtag pins. uart_rx is available on the jtag_tdi pin, and uart_tx is available on the jtag_tdo pin. the uart is primarily for debugging during development. by adding an external rs-232 transceiver, this uart enables the cyw43364 to operate as rs-232 data termination equipment (dte) for exchanging and managing data with other serial devices. it is compatible with the industry standard 16550 uart, and it provides a fifo size of 64 8 in each direction.
document number: 002-14781 rev. *c page 33 of 68 preliminary cyw43364 8. pinout and signal descriptions 8.1 ball map figure 22 shows the 74-ball wlbga ball map. figure 22. 74-ball wlbga ball map (bottom view) abcd e f gh jk l m 1 nc nc nc nc vdd_1p2 vdd_1p2 vddb_pa wlrf_2g_ elg wlrf_2g_ rf wlrf_pa_ vdd 1 2 nc nc nc nc vdd_1p2 vdd_1p2 vss vss wlrf_lna _gnd wlrf_ge neral_gn d wlrf_pa_ gnd wlrf_vd d_ 1p35 2 3 nc nc nc vddc vss vss wlrf_gpi o wlrf_vc o_gnd wlrf_xta l_ vdd1p2 3 4 nc nc nc vssc nc vddc wlrf_afe _gnd gpio_3 wlrf_xta l_gnd wlrf_xta l_xop 4 5 nc nc sys_vddi o nc nc lpo_in nc nc vssc gpio_4 gpio_2 wlrf_xta l_xon 5 6 sr_vlx pmu_avs s vout_cld o vout_lnl do gnd wcc_vddi o wl_reg_ on gpio_1 gpio_0 sdio_dat a_0 sdio_cmd clk_req 6 7 sr_pvss sr_vddb at5v ldo_vdd1 p5 vout_3p3 ldo_vdd bat5v sdio_dat a_1 sdio_dat a_3 sdio_dat a_2 sdio_clk 7 abcd e f gh jk l m
document number: 002-14781 rev. *c page 34 of 68 preliminary cyw43364 8.2 wlbga ball list in ball nu mber order with x-y coordinates ta b l e 8 provides ball numbers and names in ball number order. the table includes the x and y coordinates for a top view with a (0,0) center. table 8. cyw43364 wlbga ball list ? ordered by ball number ball number ball name x coordinate y coordinate a1 nc ?1200.006 2199.996 a2 nc ?799.992 2199.996 a3 nc ?399.996 2199.996 a4 nc 0 2199.996 a5 nc 399.996 2199.996 a6 sr_vlx 799.992 2199.978 a7 sr_pvss 1199.988 2199.978 b1 nc ?1200.006 1800 b2 nc ?799.992 1800 b3 nc ?399.996 1800 b4 nc 0 1800 b5 nc 399.996 1800 b6 pmu_avss 799.992 1799.982 b7 sr_vbat5v 1199.988 1799.982 c1 nc ?1200.006 1399.995 c2 nc ?799.992 1399.986 c3 nc ?399.996 1399.995 c4 nc 0 1399.995 c5 sys_vddio 399.996 1399.986 c6 vout_cldo 799.992 1399.986 c7 ldo_vdd15v 1199.988 1399.986 d2 nc ?799.992 999.99 d3 vddc ?399.996 999.999 d4 vssc 0 999.999 d5 nc 399.996 999.99 d6 vout_lnldo 799.992 999.99 e1 nc ?1199.988 599.994 e2 vdd_1p2 ?799.992 599.994 e3 vss ?399.996 599.994 e5 nc 399.996 599.994 e6 gnd 799.992 599.994 e7 vout_3p3 1199.988 599.994 f1 vdd_1p2 ?1199.988 199.998 f2 vdd_1p2 ?799.992 199.998
document number: 002-14781 rev. *c page 35 of 68 preliminary cyw43364 f4 nc 0 199.998 f5 lpo_in 399.996 199.998 f6 wcc_vddio 800.001 199.998 f7 ldo_vbat5v 1199.988 199.998 g1 vdd_1p2 ?1199.988 ?199.998 g2 vss ?799.992 ?199.998 g4 vddc 0 ?199.998 g5 nc 399.996 ?199.998 g6 wl_reg_on 800.001 ?199.998 h1 vddb_pa ?1199.988 ?599.994 h2 vss ?799.992 ?599.994 h3 vss ?399.996 ?599.994 h4 wlrf_afe_gnd 0 ?599.994 h5 nc 399.996 ?599.994 h6 gpio_1 800.001 ?599.994 h7 sdio_data_1 1200.006 ?599.994 j1 wlrf_2g_elg ?1199.988 ?999.99 j2 wlrf_lna_gnd ?799.992 ?999.99 j3 wlrf_gpio ?399.996 ?999.99 j5 vssc 399.996 ?999.999 j6 gpio_0 800.001 ?999.999 j7 sdio_data_3 1200.006 ?999.999 k1 wlrf_2g_rf ?1199.988 ?1399.986 k2 wlrf_general_gnd ?799.992 ?1399.986 k4 gpio_3 0 ?1399.995 k5 gpio_4 399.996 ?1399.995 k6 sdio_data_0 800.001 ?1399.995 l2 wlrf_pa_gnd ?799.992 ?1799.982 l3 wlrf_vco_gnd ?399.996 ?1799.982 l4 wlrf_xtal_gnd 0 ?1799.982 l5 gpio_2 399.996 ?1799.991 l6 sdio_cmd 800.001 ?1799.991 l7 sdio_data_2 1200.006 ?1799.991 m1 wlrf_pa_vdd ?1199.988 ?2199.978 m2 wlrf_vdd_1p35 ?799.992 ?2199.978 m3 wlrf_xtal_vdd1p2 ?399.996 ?2199.978 m4 wlrf_xtal_xop 0 ?2199.978 m5 wlrf_xtal_xon 399.996 ?2199.978 table 8. cyw43364 wlbga ball list ? ordered by ball number ball number ball name x coordinate y coordinate
document number: 002-14781 rev. *c page 36 of 68 preliminary cyw43364 m6 clk_req 800.001 ?2199.996 m7 sdio_clk 1200.006 ?2199.996 table 8. cyw43364 wlbga ball list ? ordered by ball number ball number ball name x coordinate y coordinate
document number: 002-14781 rev. *c page 37 of 68 preliminary cyw43364 8.3 wlbga ball list ordered by ball name ta b l e 9 provides the ball numbers and names in ball name order. table 9. cyw43364 wlbga ball list ? ordered by ball name ball name ball number clk_req m6 gnd e6 gpio_0 j6 gpio_1 h6 gpio_2 l5 gpio_3 k4 gpio_4 k5 ldo_vdd1p5 c7 ldo_vddbat5v f7 lpo_in f5 nc a1 nc a2 nc a3 nc a4 nc a5 nc b1 nc b2 nc b3 nc b4 nc b5 nc c1 nc c2 nc c3 nc c4 nc d2 nc d5 nc e1 nc e5 nc f4 nc g5 nc h5 pmu_avss b6 sdio_clk m7 sdio_cmd l6 sdio_data_0 k6 sdio_data_1 h7 sdio_data_2 l7 sdio_data_3 j7 sr_pvss a7 sr_vddbat5v b7 sr_vlx a6 sys_vddio c5 vdd_1p2 e2 vdd_1p2 f1 vdd_1p2 f2 vdd_1p2 g1 vddb_pa h1 vddc d3 vddc g4 vout_3p3 e7 vout_cldo c6 vout_lnldo d6 vss e3 vss g2 vss h2 vss h3 vssc d4 vssc j5 wcc_vddio f6 wl_reg_on g6 wlrf_2g_elg j1 wlrf_2g_rf k1 wlrf_afe_gnd h4 wlrf_general_gnd k2 wlrf_gpio j3 wlrf_lna_gnd j2 wlrf_pa_gnd l2 wlrf_pa_vdd m1 wlrf_vco_gnd l3 wlrf_vdd_1p35 m2 wlrf_xtal_gnd l4 wlrf_xtal_vdd1p2 m3 wlrf_xtal_xon m5 wlrf_xtal_xop m4 ball name ball number
document number: 002-14781 rev. *c page 38 of 68 preliminary cyw43364 8.4 signal descriptions ta b l e 1 0 provides the wlbga package signal descriptions. table 10. wlbga signal descriptions signal name wlbga ball type description rf signal interface wlrf_2g_rf k1 o 2.4 ghz wlan rf output port. sdio bus interface sdio_clk m7 i sdio clock input. sdio_cmd l6 i/o sdio command line. sdio_data_0 k6 i/o sdio data line 0. sdio_data_1 h7 i/o sdio data line 1. sdio_data_2 l7 i/o sdio data line 2. also used as a strapping option (see table 13 on page 42 ). sdio_data_3 j7 i/o sdio data line 3. note: per section 6 of the sdio specification, 10 to 100 k ? pull-ups are required on the four da ta lines and the cmd line. this requirement must be met during a ll operating states by using exte rnal pull-up resistors or properly programming internal sdio h ost pull-ups. wlan gpio interface wlrf_gpio j3 i/o test pin. not connected in normal operation. clocks wlrf_xtal_xon m5 o xtal oscillator output. wlrf_xtal_xop m4 i xtal oscillator input. clk_req m6 o external system clock request?used when the system clock is not provided by a dedicated crystal (for example, when a shared tcxo is used). asserted to indicate to the host that the clock is required. lpo_in f5 i external sleep clock input (32.768 khz). if an external 32.768 khz clock cannot be provided, pull this pin low. however, ble will be always on and cannot go to deep sleep. no connect nc_a1 a1 i no connect. nc_a2 a2 o no connect. nc_a3 a3 i/o no connect. nc_a4 a4 i/o no connect. nc_a5 a5 i/o no connect. nc_b1 b1 i/o no connect. nc_b2 b2 i no connect. nc_b3 b3 i/o no connect. nc_b4 b4 o no connect. nc_b5 b5 i/o no connect. nc_c1 c1 i/o no connect. nc_c2 c2 o no connect.
document number: 002-14781 rev. *c page 39 of 68 preliminary cyw43364 nc_c3 c3 o no connect. nc_c4 c4 i no connect. nc_d2 d2 o no connect. nc_e1 e1 i no connect. nc_f4 f4 i/o no connect. nc_g5 g5 i/o no connect. nc_h5 h5 i/o no connect. nc_e5 e5 n/a not used. do not connect to this pin. nc_d5 d5 n/a not used. do not connect to this pin. miscellaneous wl_reg_on g6 i used by pmu to power up or power down the internal regulators used by the wlan section. also, when deasserted, this pin holds the wlan sect ion in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. gnd_e6 e6 i tie pin e6 to ground. gpio_0 j6 i/o programmable gpio pins. this pin becomes an output pin when it is used as wlan_host_wake/ out-of-band signal. gpio_1 h6 i/o programmable gpio pins. gpio_2 l5 i/o programmable gpio pins. gpio_3 k4 i/o programmable gpio pins. gpio_4 k5 i/o programmable gpio pins. wlrf_2g_elg j1 i connect to an external inductor. see the reference schematic for details. integrated voltage regulators sr_vddbat5v b7 i sr vbat input power supply. sr_vlx a6 o cbuck switching regul ator output. see table 22 on page 53 for details of the inductor and capacitor required on this output. ldo_vddbat5v f7 i ldo vbat. ldo_vdd1p5 c7 i lnldo input. vout_lnldo d6 o output of low-noise lnldo. vout_cldo c6 o output of core ldo. vddb_pa h1 i connect to vout_3p3. vdd_1p2 g1 i connect to vout_lnldo. vdd_1p2 f2 i connect to vout_lnldo. vdd_1p2 f1 i connect to vout_lnldo. vdd_1p2 e2 i connect pin e2 to vout_lnldo. power supplies wlrf_xtal_vdd1p2 m3 i xtal oscillator supply. wlrf_pa_vdd m1 i power amplifier supply. wcc_vddio f6 i vddio input supply. connect to vddio. table 10. wlbga signal descriptions (cont.) signal name wlbga ball type description
document number: 002-14781 rev. *c page 40 of 68 preliminary cyw43364 sys_vddio c5 i vddio input su pply. connect to vddio. wlrf_vdd_1p35 m2 i lnldo input supply. vddc d3, g4 i core supply for wlan. vout_3p3 e7 o 3.3v output supply. see t he reference schematic for details. ground vss_h2 h2 i connect to ground. vss_g2 g2 i connect to ground. vss_h3 h3 i connect to ground. vss_e3 e3 i connect to ground. pmu_avss b6 i quiet ground. sr_pvss a7 i switcher-power ground. vssc d4, j5 i core ground for wlan. wlrf_afe_gnd h4 i afe ground. wlrf_lna_gnd j2 i 2.4 ghz internal lna ground. wlrf_general_gnd k2 i miscellaneous rf ground. wlrf_pa_gnd l2 i 2.4 ghz pa ground. wlrf_vco_gnd l3 i vco/lo generator ground. wlrf_xtal_gnd l4 i xtal ground. table 10. wlbga signal descriptions (cont.) signal name wlbga ball type description
document number: 002-14781 rev. *c page 41 of 68 preliminary cyw43364 8.5 wlan gpio signals and strapping options the pins listed in table 11 are sampled at power-on reset (por) to determine t he various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descriptions table. each str apping option pin has an internal pull-up (pu) or pull-down (pd) r esistor that determines the default mode. to change the mode, connect an exte rnal pu resistor to vddio or a pd resistor to ground using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. 8.6 chip debug options the chip can be accessed for debugging via the jtag interface, multiplexed on the sdio_data_0 through sdio_data_3 (and sdio_clk) i/o depending on the boot strap state of gpio_1 and gpio_2. ta b l e 1 2 shows the debug options of the device. table 11. gpio functions and strapping options pin name wlbga pin # default function description sdio_data_2 l7 1 wlan host interface select this pin selects the wlan host interface mode. the default is sdio. for gspi, pull this pin low. table 12. chip debug options jtag_sel gpio_2 gpio_1 function sdio i/o pad function 0 0 0 normal mode sdio 0 0 1 jtag over sdio jtag 0 1 1 swd over gpio_1/gpio_2 sdio
document number: 002-14781 rev. *c page 42 of 68 preliminary cyw43364 8.7 i/o states the following notations are used in table 13 : i: input signal o: output signal i/o: input/output signal pu = pulled up pd = pulled down nopull = neither pulled up nor pulled down table 13. i/o states name i/o keeper active mode low power state/ sleep (all power present) power-down (wl_reg_on=0 bt_reg_on=don?t care) out-of-reset; (wl_reg_on=1; bt_reg_on=don?t care) (wl_reg_on=1 and bt_reg_on=0) and vddios are present (wl_reg_on=0 and bt_reg_on=1) and vddios are present power rail wl_reg_on i n input; pd (pull-down can be disabled) input; pd (pull-down can be disabled) input; pd (of 200k) input; pd (200k) input; pd (200k) ? ? clk_req i/o y open drain or push-pull (programmable). active high. open drain or push-pull (programmable). active high pd open drain, active high. open drain, active high. open drain, active high. wcc_vddio sdio_data_0 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_data_1 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_data_2 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_data_3 i/o n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> pu sdio mode -> nopull input; pu wcc_vddio sdio_cmd i/o n sdio mode -> nopull sdio mode -> nopull sd io mode -> nopull sdio mo de -> pu sdio mode -> nopull input; pu wcc_vddio sdio_clk i n sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull sdio mode -> nopull input wcc_vddio jtag_sel i y pd pd high-z, nopull input, pd pd input, pd wcc_vddio gpio_0 i/o y tbd active mode high-z, nopull a input, sdio oob int, nopull active mode input, nopull wcc_vddio gpio_1 i/o y tbd active mode high-z, nopull a input, pd active mode input, strap, pd wcc_vddio gpio_2 i/o y tbd active mode high-z, nopull a input, gci gpio[7], nopull active mode input, strap, nopull wcc_vddio gpio_3 i/o y tbd active mode high-z, nopull a input, gci gpio[0], pu active mode input, pu wcc_vddio gpio_4 i/o y tbd active mode high-z, nopull a input, gci gpio[1], pu active mode input, pu wcc_vddio
document number: 002-14781 rev. *c page 43 of 68 preliminary cyw43364 note: 1. keeper column: n = pad has no keeper. y = pad has a keeper. k eeper is always active except in the power-down state. 2. if there is no keeper, and it is an input and there is nopull, then the pad should be driven to prevent leakage due to a floati ng pad (e.g., sdio_clk). 3. in the power-down state (xx_reg_on = 0): high-z; nopu ll => the pad is disabled bec ause power is not supplied. 4. depending on whether the pcm interface is enabled and the configurat ion is master or slave mode, it can be either an output or input. 5. depending on whether the i 2 s interface is enabled and the configuration is master or slave mode, it can be either an output or input. 6. the gpio pull states for the active and low -power states are hardware defaults. they can all be subsequently programmed as pull -ups or pull-downs. 7. regarding gpio pins, the followi ng are the pull-up and pull-down values for both 3.3v and 1.8v vddio: minimum (k ? ) typical (k ? ) maximum (k ? ) 3.3v vddio pull-downs: 51.5 44.5 38 3.3v vddio pull-ups: 37.4 39.5 44.5 1.8v vddio pull-downs: 64 83 116 1.8v vddio pull-ups: 65 86 118 a. the gpio pull states for the active and low-power states are hardware defaults. t hey can all be subsequently programmed as a pull-up or pull-down. table 13. i/o states (cont.) name i/o keeper active mode low power state/ sleep (all power present) power-down (wl_reg_on=0 bt_reg_on=don?t care) out-of-reset; (wl_reg_on=1; bt_reg_on=don?t care) (wl_reg_on=1 and bt_reg_on=0) and vddios are present (wl_reg_on=0 and bt_reg_on=1) and vddios are present power rail
document number: 002-14781 rev. *c page 44 of 68 preliminary cyw43364 9. dc characteristics note: values in this data sheet are design goals and are subject to change based on the results of device characterization. 9.1 absolute maximum ratings 9.2 environmental ratings the environmental ratings are shown in ta b l e 1 5 . caution: the absolute maximum ratings in table 14 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operation is not guaranteed under these conditions. excluding vbat, operation at the absol ute maximum conditions for extended per iods can adversely affect long-term reliability of the device. table 14. absolute maximum ratings rating symbol value unit dc supply for vbat and pa driver supply vbat ?0.5 to +6.0 a a. continuous operation at 6.0v is supported. v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/os vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo and lnldo ? ?0.5 to 1.575 v dc supply voltage for rf analog vddrf ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v maximum undershoot voltage for i/o b b. duration not to exceed 25% of the duty cycle. v undershoot ?0.5 v maximum overshoot voltage for i/o b v overshoot vddio + 0.5 v maximum junction temperature t j 125 c table 15. environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?30 to +70c a a. functionality is guaranteed, but specificat ions require derating at extreme temperatur es (see the specification tables for de tails). ? c operation storage temperature ?40 to +125c ? c? relative humidity less than 60 % storage less than 85 % operation
document number: 002-14781 rev. *c page 45 of 68 preliminary cyw43364 9.3 electrostatic discharge specifications extreme caution must be exercised to prev ent electrostatic discharge (esd) damage. pr oper use of wrist and heel grounding strap s to discharge static electricity is required when handling these devices. always store unused material in its antistatic packagi ng. 9.4 recommended operating conditions and dc characteristics functional operation is not guarant eed outside the limits shown in ta b l e 1 7 , and operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 16. esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model contact discharge per jedec eid/jesd22-a114 1250 v machine model (mm) esd_hand_mm machine model contact 50 v cdm esd_hand_cdm charged device model contact discharge per jedec eia/jesd22- c101 300 v table 17. recommended operating conditions and dc characteristics element symbol value unit minimum typical maximum dc supply voltage for vbat vbat 3.0 a ?4.8 b v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v dc supply voltage for digital i/o vddio, vddio_sd 1.71 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf 3.13 3.3 3.46 v external tssi input tssi 0.15 ? 0.95 v internal por threshold vth_por 0.4 ? 0.7 v sdio interface i/o pins for vddio_sd = 1.8v: input high voltage vih 1.27 ? ? v input low voltage vil ? ? 0.58 v output high voltage @ 2 ma voh 1.40 ? ? v output low voltage @ 2 ma vol ? ? 0.45 v for vddio_sd = 3.3v: input high voltage vih 0.625 vddio ? ? v input low voltage vil ? ? 0.25 vddio v output high voltage @ 2 ma voh 0.75 vddio ? ? v output low voltage @ 2 ma vol ? ? 0.125 vddio v other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ? ? v input low voltage vil ? ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ? ? v output low voltage @ 2 ma vol ? ? 0.45 v for vddio = 3.3v:
document number: 002-14781 rev. *c page 46 of 68 preliminary cyw43364 input high voltage vih 2.00 ? ? v input low voltage vil ? ? 0.80 v output high voltage @ 2 ma voh vddio ? 0.4 ? ? v output low voltage @ 2 ma vol ? ? 0.40 v rf switch control output pins c for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ? v output low voltage @ 2 ma vol ? ? 0.40 v input capacitance c in ?? 5pf a. the cyw43364 is functional across this range of voltages. howe ver, optimal rf performance specified in the data sheet is guar anteed only for 3.2v < vbat < 4.8v. b. the maximum continuous voltage is 4.8v. voltages up to 6.0v fo r up to 10 seconds, cumulative duration over the lifetime of th e device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative dura tion over the lifetime of the device are allowed. c. programmable 2 ma to 16 ma drive strength. default is 10 ma. table 17. recommended operating conditions and dc characteristics (cont.) element symbol value unit minimum typical maximum
document number: 002-14781 rev. *c page 47 of 68 preliminary cyw43364 10. wlan rf specifications the cyw43364 includes an integrated direct conversion radio t hat supports the 2.4 ghz band. this section describes the rf characteristics of the 2.4 ghz radio. note: values in this data sheet are design goals and may change based on device characterization results. unless otherwise stated, the specifications in this section apply when the op erating conditions are wit hin the limits specified in table 15 on page 44 and table 17 on page 45 . functional operation outside these limits is not guaranteed. typical values apply for the following conditions: vbat = 3.6v. ambient temperature +25c. figure 23. rf port location note: all specifications appl y at the chip port unle ss otherwise specified. 10.1 2.4 ghz band general rf specifications table 18. 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s tx rx c2 10 pf l1 4.7 nh c1 10 pf filter chip port antenna port cyw43364
document number: 002-14781 rev. *c page 48 of 68 preliminary cyw43364 10.2 wlan 2.4 ghz receiver performance specifications note: unless otherwise specified, the specifications in table 19 are measured at the chip port (for the location of the chip port, see figure 23 on page 47 ). table 19. wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz rx sensitivity (8% per for 1024 octet psdu) a 1 mbps dsss ?97.5 ?99.5 ? dbm 2 mbps dsss ?93.5 ?95.5 ? dbm 5.5 mbps dsss ?91.5 ?93.5 ? dbm 11 mbps dsss ?88.5 ?90.5 ? dbm rx sensitivity (10% per for 1000 octet psdu) at wlan rf port a 6 mbps ofdm ?91.5 ?93.5 ? dbm 9 mbps ofdm ?90.5 ?92.5 ? dbm 12 mbps ofdm ?87.5 ?89.5 ? dbm 18 mbps ofdm ?85.5 ?87.5 ? dbm 24 mbps ofdm ?82.5 ?84.5 ? dbm 36 mbps ofdm ?80.5 ?82.5 ? dbm 48 mbps ofdm ?76.5 ?78.5 ? dbm 54 mbps ofdm ?75.5 ?77.5 ? dbm rx sensitivity (10% per for 4096 octet psdu). defined for default parameters: gf, 800 ns gi. 20 mhz channel spacing for all mcs rates (mixed mode) 256-qam, r = 5/6 ?67.5 ?69.5 ? dbm 256-qam, r = 3/4 ?69.5 ?71.5 ? dbm mcs7 ?71.5 ?73.5 ? dbm mcs6 ?73.5 ?75.5 ? dbm mcs5 ?74.5 ?76.5 ? dbm mcs4 ?79.5 ?81.5 ? dbm mcs3 ?82.5 ?84.5 ? dbm mcs2 ?84.5 ?86.5 ? dbm mcs1 ?86.5 ?88.5 ? dbm mcs0 ?90.5 ?92.5 ? dbm
document number: 002-14781 rev. *c page 49 of 68 preliminary cyw43364 blocking level for 3 db rx sensi- tivity degradation (without external filtering) 704?716 lte ? ?13 ? dbm 777?787 lte ? ?13 ? dbm 776?794 mhz cdma2000 ? ?13.5 ? dbm 815?830 lte ? ?12.5 ? dbm 816?824 cdma2000 ? ?13.5 ? dbm 816?849 lte ? ?11.5 ? dbm 824?849 wcdma ? ?11.5 ? dbm 824?849 cdma2000 ? ?12.5 ? dbm 824?849 lte ? ?11.5 ? dbm 824?849 gsm850 ? ?8 ? dbm 830?845 lte ? ?11.5 ? dbm 832?862 lte ? ?11.5 ? dbm 880?915 wcdma ? ?10 ? dbm 880?915 lte ? ?12 ? dbm 880?915 e-gsm ? ?9 ? dbm 1710?1755 wcdma ? ?13 ? dbm 1710?1755 lte ? ?14.5 ? dbm 1710?1755 cdma2000 ? ?14.5 ? dbm 1710?1785 wcdma ? ?13 ? dbm 1710?1785 lte ? ?14.5 ? dbm 1710?1785 gsm1800 ? ?12.5 ? dbm 1850?1910 gsm1900 ? ?11.5 ? dbm 1850?1910 cdma2000 ? ?16 ? dbm 1850?1910 wcdma ? ?13.5 ? dbm 1850?1910 lte ? ?16 ? dbm 1850?1915 lte ? ?17 ? dbm 1920?1980 wcdma ? ?17.5 ? dbm blocking level for 3 db rx sensi- tivity degradation (without external filtering) (cont.) 1920?1980 cdma2000 ? ?19.5 ? dbm 1920?1980 lte ? ?19.5 ? dbm 2300?2400 lte ? ?44 ? dbm 2500?2570 lte ? ?43 ? dbm 2570?2620 lte ? ?34 ? dbm 5g (wlan) wlan ? >?4 ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?6 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?12 ? ? dbm @ 6?54 mbps (10% per, 1000 octets) ?15.5 ? ? dbm table 19. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14781 rev. *c page 50 of 68 preliminary cyw43364 adjacent channel rejection- dsss. (difference between interfering and desired signal [25 mhz apart] at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes.) 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection- ofdm. (difference between interfering and desired signal (25 mhz apart) at 10% per for 1000 b octet psdu with desired signal level as specified in condition/ notes.) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db rcpi accuracy c range ?98 dbm to ?75 dbm ?3 ? 3 db range above ?75 dbm ?5 ? 5 db return loss zo = 50 ? across the dynamic range. 10 ? ? db a. optimal rf performance, as specified in this data sheet, is guaranteed on ly for temperatures between ?10c and 55c. b. for 65 mbps, the size is 4096. c. the minimum and maximum values shown have a 95% confidence level. table 19. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14781 rev. *c page 51 of 68 preliminary cyw43364 10.3 wlan 2.4 ghz transmitter performance specifications note: unless otherwise specified, the specifications in table 19 are measured at the chip port (for the location of the chip port, see figure 23 on page 47 ). table 20. wlan 2.4 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz transmitted power in cellular and wlan 5g band (at 21 dbm, 90% duty cycle, 1 mbps cck). 776?794 mhz cdma2000 ? ?167.5 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?163.5 ? dbm/hz 1450?1495 dab ? ?154.5 ? dbm/hz 1570?1580 mhz gps ? ?152.5 ? dbm/hz 1592?1610 mhz glonass ? ?149.5 ? dbm/hz 1710?1800 dsc-1800-uplink ? ?145.5 ? dbm/hz 1805?1880 mhz gsm 1800 ? ?143.5 ? dbm/hz 1850?1910 mhz gsm 1900 ? ?140.5 ? dbm/hz 1910?1930 mhz tdscdma,lte ? ?138.5 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ??139 ?dbm/hz 2010?2075 mhz tdscdma ? ?127.5 ? dbm/hz 2110?2170 mhz wcdma ? ?124.5 ? dbm/hz 2305?2370 lte band 40 ? ?104.5 ? dbm/hz 2370?2400 lte band 40 ? ?81.5 ? dbm/hz 2496?2530 lte band 41 ? ?94.5 ? dbm/hz 2530?2560 lte band 41 ? ?120.5 ? dbm/hz 2570?2690 lte band 41 ? ?121.5 ? dbm/hz 5000?5900 wlan 5g ? ?109.5 ? dbm/hz harmonic level (at 21 dbm with 90% duty cycle, 1 mbps cck) 4.8-5.0 ghz 2nd harmonic ? ?26.5 ? dbm/ mhz 7.2-7.5 ghz 3rd harmonic ? ?23.5 ? dbm/ mhz 9.6-10 ghz 4th harmonic ? ?32.5 ? dbm/ mhz tx power at the chip port for the highest power level setting at 25c, vba = 3.6v, and spectral mask and evm compliance a, b evm does not exceed ieee 802.11b (dsss/cck) ?9 db 21 ? ? dbm ofdm, bpsk ?8 db 20.5 ? ? dbm ofdm, qpsk ?13 db 20.5 ? ? dbm ofdm, 16-qam ?19 db 20.5 ? ? dbm ofdm, 64-qam (r = 3/4) ?25 db 18 ? ? dbm ofdm, 64-qam (r = 5/6) ?27 db 17.5 ? ? dbm ofdm, 256-qam (r = 5/6) ?32 db 15 ? ? dbm
document number: 002-14781 rev. *c page 52 of 68 preliminary cyw43364 10.4 general spurious emissions specifications tx power control dynamic range ?9??db closed loop tx power variation at highest power level setting across full temperature and voltage range. applies across 5 to 21 dbm output power range. ??1.5db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss zo = 50 4 6 ? db load pull variation for output power, evm, and adjacent channel power ratio (acpr) vswr = 2:1. evm degradation ? 3.5 ? db output power variation ? 2 ? db acpr-compliant power level ?15 ?dbm vswr = 3:1. evm degradation ? 4 ? db output power variation ? 3 ? db acpr-compliant power level ?15 ?dbm a. tx power for channel 1 and channel 11 is specified separately by nonvolatile memo ry parameters to ensure band-edge compliance . b. optimal rf performance, as specified in this data sheet, is guaranteed on ly for temperatures between ?10c and 55c. table 21. general spurious emissions specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz general spurious emissions tx emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?44 ?41 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?68 ?65 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm rx/standby emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?99 ?96 dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?54 ?51 dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?88 ?85 dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?88 ?85 dbm note: the specifications in this ta ble apply at the chip port. table 20. wlan 2.4 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-14781 rev. *c page 53 of 68 preliminary cyw43364 11. internal regulator electrical specifications note: values in this data sheet are design goals and are subject to change based on device characterization results. functional operation is not guarant eed outside of the specification limits provided in this section. 11.1 core buck switching regulator table 22. core buck switching regulator (cbuck) specifications specification notes min. typ. max. units input supply voltage (dc) dc voltage rang e inclusive of disturbances. 2.4 3.6 4.8 a a. the maximum continuous voltage is 4.8v. voltages up to 6.0v for up to 10 seconds, cumulative duration, over the lifetime of t he device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v pwm mode switching frequency ccm, load > 100 ma vbat = 3.6v. ? 4 ? mhz pwm output current ? ? ? 370 ma output current limit ? ? 1400 ? ma output voltage range programmable, 30 mv steps. default = 1.35v. 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode. ?4 ? 4 % pwm ripple voltage, static measure with 20 mhz bandwidth limit. static load, max. ripple based on vbat = 3.6v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor l > 1.05 h, cap + board total-esr < 20 m ? , c out > 1.9 f, esl<200 ph ? 7 20 mvpp pwm mode peak efficiency peak efficiency at 200 ma load, inductor dcr = 200 m ? , vbat = 3.6v, vout = 1.35v ?85? % pfm mode efficiency 10 ma load current, inductor dcr = 200 m ? , vbat = 3.6v, vout = 1.35v ?77? % start-up time from power down vddio already on and steady. time from reg_on rising edge to cldo reaching 1.2v ? 400 500 s external inductor 0603 size, 2.2 h 20%, dcr = 0.2 ? 25% ?2.2?h external output capacitor ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 4.7 f 20%, 10v 2.0 b b. minimum capacitor value refers to the re sidual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 c c. total capacitance includes those connected at the far end of the active load. f external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 4.7 f 20%, 10v 0.67 b 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s
document number: 002-14781 rev. *c page 54 of 68 preliminary cyw43364 11.2 3.3v ldo (ldo3p3) table 23. ldo3p3 specifications specification notes min. typ. max. units input supply voltage, v in min. = v o + 0.2v = 3.5v dropout voltage requirement must be met under maximum load for performance specifications. 3.1 3.6 4.8 a a. the maximum continuous voltage is 4.8v. voltages up to 6.0v fo r up to 10 seconds, cumulative duration, over the lifetime of t he device are allowed. voltages as high as 5.0v for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. v output current ? 0.001 ? 450 ma nominal output voltage, v o default = 3.3v. ? 3.3 ? v dropout voltage at max. load. ? ? 200 mv output voltage dc accuracy includes line/load regulation. ?5 ? +5 % quiescent current no load ? 66 85 a line regulation v in from (v o + 0.2v) to 4.8v, max. load ? ? 3.5 mv/v load regulation load from 1 ma to 450 ma ? ? 0.3 mv/ma psrr v in v o + 0.2v, v o = 3.3v, c o = 4.7 f, max. load, 100 hz to 100 khz 20 ? ? db ldo turn-on time chip already powered up. ? 160 250 s external output capacitor, c o ceramic, x5r, 0402, (esr: 5 m ? ?240 m ? ), 10%, 10v 1.0 b b. minimum capacitor value refers to the re sidual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 5.64 f external input capacitor for sr_vddbata5v pin (shared with band gap) ceramic, x5r, 0402, (esr: 30m-200 m ? ), 10%, 10v. not needed if sharing vbat capacitor 4.7 f with sr_vddbatp5v. ?4.7? f
document number: 002-14781 rev. *c page 55 of 68 preliminary cyw43364 11.3 cldo table 24. cldo specifications specification notes min. typ. max. units input supply voltage, v in min. = 1.2 + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current 7 0.2 ? 200 ma output voltage, v o programmable in 10 mv steps. default = 1.2.v 0.95 1.2 1.26 v dropout voltage at max. load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 13 ? a 200 ma load ? 1.24 ? ma line regulation v in from (v o + 0.15v) to 1.5v, maximum load ??5mv/v load regulation load from 1 ma to 300 ma ? 0.02 0.05 mv/ma leakage current power down ? 5 20 a bypass mode ? 1 3 a psrr @1 khz, vin 1.35v, c o = 4.7 f 20 ? ? db start-up time of pmu vddio up and steady. time from the reg_on rising edge to the cldo reaching 1.2v. ? ? 700 s ldo turn-on time ldo turn-on time wh en rest of the chip is up. ? 140 180 s external output capacitor, c o to t a l e s r : 5 m ? ?240 m ? 1.1 a a. minimum capacitor value refers to the re sidual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ?12.2f
document number: 002-14781 rev. *c page 56 of 68 preliminary cyw43364 11.4 lnldo table 25. lnldo specifications specification notes min. typ. max. units input supply voltage, vin min. v in = v o + 0.15v = 1.35v (where v o = 1.2v) dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 10 12 a max. load ? 970 990 a line regulation v in from (v o + 0.15v) to 1.5v, 200 ma load ?? 5mv/v load regulation load from 1 ma to 200 ma: v in (v o + 0.12v) ? 0.025 0.045 mv/ma leakage current power-down, junction temp. = 85c ? 5 20 a output noise @30 khz, 60?150 ma load c o = 2.2 f @100 khz, 60?150 ma load c o = 2.2 f ? ? 60 35 ? psrr @1 khz, v in (v o + 0.15v), c o = 4.7 f 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 0.5 a a. minimum capacitor value refers to the re sidual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ? 1 2.2 f nv/ hz
document number: 002-14781 rev. *c page 57 of 68 preliminary cyw43364 12. system power consumption note : the values in this data sheet are design goals and are subjec t to change based on device characterization.unless otherwise stat ed, these values apply for the conditions specified in table 17 on page 45 . 12.1 wlan current consumption table 26 shows typical currents consumed by the cyw43364?s wlan section. 12.1.1 2.4 ghz mode table 26. 2.4 ghz mode wlan power consumption mode rate vbat = 3.6v, vddio = 1.8v, ta 25c vbat (ma) vio (a) sleep modes leakage (off) n/a 0.0035 0.08 sleep (idle, unassociated) a a. device is initialized in sleep mode, but not associated. n/a 0.0058 80 sleep (idle, associated, inter-beacons) b b. device is associated, and then enters power save mode (idle between beacons). rate 1 0.0058 80 ieee power save pm1 dtim1 (avg.) c c. beacon interval = 100 ms; beacon duration = 1 ms @ 1 mbps (integrated sleep + wakeup + beacon). rate 1 1.05 74 ieee power save pm1 dtim3 (avg.) d d. beacon interval = 300 ms; beacon duration = 1 ms @ 1 mbps (integrated sleep + wakeup + beacon). rate 1 0.35 86 ieee power save pm2 dtim1 (avg.) c rate 1 1.05 74 ieee power save pm2 dtim3 (avg.) d rate 1 0.35 86 active modes rx listen mode e e. carrier sense (cca) when no carrier present. n/a 37 12 rx active (at ?50dbm rssi) f f. tx output power is measured on the chip-out side; duty cycle =1 00%. tx active mode is measured in packet engine mode (pseudo- random data) rate 1 39 12 rate 11 40 12 rate 54 40 12 rate mcs7 41 12 tx f rate 1 @ 20 dbm 320 15 rate 11 @ 18 dbm 290 15 rate 54 @ 15 dbm 260 15 rate c7 @ 15 dbm 260 15
document number: 002-14781 rev. *c page 58 of 68 preliminary cyw43364 13. interface timing an d ac characteristics note: values in this data sheet are design goals and are subject to change based on the results of device characterization. unless otherwise stated, the specifications in this section apply when the op erating conditions are wit hin the limits specified in table 15 on page 44 and table 17 on page 45 . functional operation outside of these limits is not guaranteed. 13.1 sdio default mode timing sdio default mode timing is shown by the combination of figure 24 and table 27 on page 59 . figure 24. sdio bus timing (default mode) t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk
document number: 002-14781 rev. *c page 59 of 68 preliminary cyw43364 13.2 sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 25 and table 28 . figure 25. sdio bus timing (high-speed mode) table 27. sdio bus timing a parameters (default mode) a. timing is based on cl ? 40 pf load on command and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min (vih) = 0.7 vddio and max (vil) = 0.2 vddio. frequency?data transfer mode fpp 0 ? 25 mhz frequency?identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock fall time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu 5 ? ? ns input hold time tih 5 ? ? ns outputs: cmd, dat (referenced to clk) output delay time?data transfer mode todly 0 ? 14 ns output delay time?identification mode todly 0 ? 50 ns t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% vdd t oh sdio_clk
document number: 002-14781 rev. *c page 60 of 68 preliminary cyw43364 13.3 gspi signal timing the gspi device always samples data on the rising edge of the clock. figure 26. gspi timing table 28. sdio bus timing a parameters (h igh-speed mode) a. timing is based on cl ? 40 pf load on command and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min (vih) = 0.7 vddio and max (vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 7 ? ? ns clock high time twh 7 ? ? ns clock rise time ttlh ? ? 3 ns clock fall time tthl ? ? 3 ns inputs: cmd, dat (referenced to clk) input setup time tisu 6 ? ? ns input hold time tih 2 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf t4 t5 t1 t2 t 3 t7 t6 t9 t8 spi_clk spi_din spi_dout (falling ? edge)
document number: 002-14781 rev. *c page 61 of 68 preliminary cyw43364 13.4 jtag timing table 29. gspi timing parameters parameter symbol minimum maximum units note clock period t1 20.8 ? ns f max = 50 mhz clock high/low t2/t3 (0.45 t1) ? t4 (0.55 t1) ? t4 ns ? clock rise/fall time t4/t5 ? 2.5 ns ? input setup time t6 5.0 ? ns setup time, simo valid to spi_clk active edge input hold time t7 5.0 ? ns hold time, spi_clk active edge to simo invalid output setup time t8 5.0 ? ns setup time, somi valid before spi_clk rising output hold time t9 5.0 ? ns hold time, spi_clk active edge to somi invalid csx to clock a ? 7.86 ? ns csx fall to 1st rising edge clock to csx c ? ? ? ns last falling edge to csx high a. spi_csx remains active for entire duration of gspi read/write/write_read transaction (that is, overall words for multiple wor d transaction). table 30. jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ?
document number: 002-14781 rev. *c page 62 of 68 preliminary cyw43364 14. power-up sequence and timing 14.1 sequencing of reset and regulator control signals the cyw43364 wl_reg_on signal allows the host to control powe r consumption by enabling or disabling the wlan and internal regulator blocks. these signals are described below. additionally, diagrams are provided to indicate proper sequencing of the s ignals for various operational states (see figure 27 and figure 28 ). the timing values indicated are minimum required values; longer delays are also acceptable. note : the cyw43364 has an internal power-on reset (por) circuit. the de vice will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold (see table 17 on page 45 ). wait at least 150 ms after vddc and vddio are available before initiating sdio accesses. vbat and vddio should not rise faster than 40 s. vbat should be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high. 14.1.1 control signal timing diagrams figure 27. wlan = on figure 28. wlan = off 32.678 khz sleep clock vbat vddio wl_reg_on 90% of vh ~ 2 sleep cycles 32.678 khz sleep clock vbat vddio wl_reg_on
document number: 002-14781 rev. *c page 63 of 68 preliminary cyw43364 15. package information 15.1 package thermal characteristics 15.1.1 junction temperature es timation and psi versus theta jc package thermal characterization parameter psi-jt ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta-j c ( ? jc ). the reason for this is ? jc assumes that all the power is dissipated through the top surface of the package case. in actual applicat ions, some of the power is dissipated through the bottom and sid es of the package. ? jt takes into account power dissipated through the top, bo ttom, and sides of the package . the equation for calculating the device junction temperature is as follows: t j = t t + p ?? jt where: t j = junction temperature at steady-state condition, c t t = package case top center temperature at steady-state condition, c p = device power dissipation, watts ? jt = package thermal characteristics (no airflow), c/w table 31. package thermal characteristics a a. no heat sink, ta = 70c. this is an estimate based on a 4-la yer pcb that conforms to eia/jesd51?7 (101.6 mm x 114.3 mm x 1.6 mm) and p = 1.2w continuous dissipation. characteristic value in still air ? ja (c/w) 53.11 ? jb (c/w) 13.14 ? jc (c/w) 6.36 ? jt (c/w) 0.04 ? jb (c/w) 14.21 maximum junction temperature t j (c) b b. absolute junction temperature limits maintained through active thermal monitoring and dynamic tx duty cycle limiting. 125 maximum power dissipation (w) 1.2
document number: 002-14781 rev. *c page 64 of 68 preliminary cyw43364 16. mechanical information figure 29 shows the mechanical drawing for the cyw43364 wlbga package. figure 29. 74-ball wlbga mechanical information
document number: 002-14781 rev. *c page 65 of 68 preliminary cyw43364 figure 30. wlbga package keep-out areas?top view with the bumps facing down
document number: 002-14781 rev. *c page 66 of 68 preliminary cyw43364 17. ordering information part number a a. add a ?t? to the end of the part number to specify ?tape and reel.? package description operating ambi- ent temperature cyw43364kubg 74-ball wlbga halogen-free package (4.87 mm x 2.87 mm, 0.40 pitch) 2.4 ghz single-band wlan ieee 802.11n ?30c to +70c
document number: 002-14781 rev. *c page 67 of 68 preliminary cyw43364 document history document title: cyw43364 single-chi p ieee 802.11 b/g/n mac/baseband/radio document number: 002-14781 revision ecn orig. of change submission date description of change ** ? ? 12/08/14 43364-ds100-r initial release *a ? ? 08/06/15 43364-ds101-r updated: figure 3: ?typical power topology (1 of 2),? on page 14. figure 4: ?typical power topology (2 of 2),? on page 15. figure 22: ?74-ball wlbga ball map (bottom view),? on page 44. table 7: ?BCM43364 wlbga ball list ? ordered by ball number,? on page 45. table 8: ?BCM43364 wlbga ball list ? ordered by ball name,? on page 48. table 9: ?wlbga signal descriptions,? on page 49. table 12: ?i/o states,? on page 53. table 18: ?wlan 2.4 ghz receiver pe rformance specifications,? on page 59. table 19: ?wlan 2.4 ghz transmitter pe rformance specifications,? on page 62. table 25: ?2.4 ghz mode wlan power consumption,? on page 70. *b ? ? 10/05/15 43364-ds102-r updated: table 10, ?wlbga signal descriptions,? on page 38 table 13, ?i/o states,? on page 42 *c 5525641 utsv 11/18/16 updated to cypress format
document number: 002-14781 rev. *c revised november 18, 2016 page 68 of 68 preliminary cyw43364 ? cypress semiconductor corporation, 2014-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support 68

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